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| DATA SHEET MOS INTEGRATED CIRCUIT PD16344 64-BIT AC-PDP DRIVER DESCRIPTION The PD16344 is a row driver for an AC plasma display panel (PDP) using high breakdown voltage CMOS process. The PD16344 consists of a 64-bit bi-directional shift register, latch circuit and high breakdown voltage CMOS driver section. The logic section operates on a 5-V power supply so that it can be connected directly to a gate array and microcomputer (CMOS level input). The driver section provides high breakdown voltage output of 120 V and +400 mA, -150 mA. Both the logic and driver sections are constructed by CMOS, witch allows operation with low power consumption. FEATURES * High voltage full CMOS process * High breakdown voltage, high current output (Maximum rating: 120 V, +400 mA, -150 mA) * 64-bit bi-directional shift register on chip * Data control by transfer clock (external) and latch * High-speed data transfer capability (fCLK = 12 MHz MAX.: when cascaded) * Wider operating ambient temperature (TA = -40C to 85C) ORDERING INFORMATION Part number Package 100-pin plastic QFP(14 x 20) PD16344GF-3BA The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14575EJ2V0DS00 (2nd edition) Date Published November 2000 NS CP(K) Printed in Japan The mark 5 shows major revised points. 1999, 2000 PD16344 1. BLOCK DIAGRAM (Shift register: 64-bit) /OE /LBLK HBLK LE1 LE2 VDD2 DA A CLK A SR S1 LE1, LE2 S1 S2 VSS2 S3 DK S4 L1 O1 CLK S2 /CLR CLR S3 S4 S61 S62 S63 S64 B B S61 S62 S63 S64 L64 O64 VDD2 DA VSS2 SR: 64-bit shift register DK Remark /xxx indicates active low signal. 2 Data Sheet S14575EJ2V0DS PD16344 2. PIN CONFIGURATION (Top view) PD16344GF-3BA /LBLK HBLK /CLR DK1 CLK DK2 31 VDD2 VDD1 VDD2 DA1 DA2 VSS2 VSS1 VSS2 R,/L LE1 LE2 /OE A O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 50 B 51 30 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 80 100 81 1 O35 VSUB VSUB DK1 DA1 DA1 VDD2 VDD1 VSUB VSUB VDD2 DA2 DA2 DK2 VSS2 VSS1 VSS2 O31 O32 O33 Caution Be sure to use all of the VDD1, VDD2, VSS1, and VSS2 pins. Use VSS1, VSS2, and VSUB at the same potential. O34 Data Sheet S14575EJ2V0DS 3 PD16344 3. PIN FUNCTIONS Pin Symbol HBLK LE1, LE2 Pin Name High blanking input Latch strobe input Pin Number 45 35, 39 Description All output = H, when HBLK = H L = Through, H = Data preservation LE1: Latch of odd register LE2: Latch of even register A B CLK /OE /LBLK R,/L Left data input Right data input Clock input Enable input Low blanking input Shift control input 42 40 38 46 44 36 When R,/L = L: A: Input When R,/L = H: A: Output B: Output B: Input Shift performed on a rising edge L = All output, high-impedance All output = L, when /LBLK = L L = Left shift mode H = Right shift mode A O1 ... O64 B B O64 ... O1 A /CLR O1 to O64 Register clear High withstand voltage output 43 1 to 30, 51 to 82, 99, 100, L = All shift register data cleared (L level clear) 110 V, +300 mA, -100 mA DA1 DK1 DA2 DK2 VDD1 VDD2 VSS1 VSS2 VSUB Diode source 1 Diode sink 1 Diode source 2 Diode sink 2 Logic section power supply Driver section power supply Logic ground Driver ground Substrate ground 49, 84, 85 50, 83 32, 96, 97 31, 98 41, 90 34, 47, 87, 94 37, 91 33, 48, 86, 95 88, 89, 92, 93 Diode source pin for O1 to O32 Diode sink pin for O1 to O32 Diode source pin for O33 to O64 Diode sink pin for O33 to O64 5 V 10 % 30 to 110 V Connected to system GND Connected to system GND Connected to system GND 4 Data Sheet S14575EJ2V0DS PD16344 4. TRUTH TABLE Shift Register Section Input R,/L L L H H x CLK H or L H or L x Output Note2 Output /CLR A Input B Output Note1 Shift Register Left shift operation performed Hold Right shift operation performed Hold All registers = L H H H H Output Input Output x x L Notes 1. On the rising edge of the clock, the data of S63 is shifted to S64, and data is output from B. 2. On the rising edge of the clock, the data of S2 is shifted to S1, and data is output from A. Latch Section LE H L Operation (Ln) Holds and outputs data immediately before LE becomes H. Outputs shift register data. Driver Section A (B) x x x L H x HBLK H x x L L L /LBLK H L x H H H /OE H H L H H H /CLR x x x H H L Driver Output State All driver output: H All driver output: L Note All driver output: High impedance H L H Note The capacity of the Nch transistor decreases to about 1/4 of the normal state for a certain period of time at the falling edge of /LBLK. Refer to Switching Characteristics Waveform on 8. ELECTRICAL SPECIFICATIONS. Remark x: H or L, H: High level, L: Low level Data Sheet S14575EJ2V0DS 5 PD16344 5. TIMING CHART (R,/L ="L", when left shift mode) 1 CLK A (B) /CLR LE1,2 HBLK /LBLK /OE 2 3 4 5 6 7 8 63 64 65 66 67 68 69 70 71 S1 (S64) S2 (S63) S3 (S62) S4 (S61) S5 (S60) S6 (S59) S63 (S2) S64 (S1) B (A) O1 (O64) O2 (O63) O3 (O62) O4 (O61) O63 (O2) O64 (O1) Remark In the parentheses: when R,/L=H 6 Data Sheet S14575EJ2V0DS PD16344 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C, VSS1 = VSS2 = 0 V) Parameter Logic section supply voltage Driver section supply voltage Logic section input voltage Driver section output current Diode peak forward current Allowed package loss Operating ambient temperature Storage temperature Symbol VDD1 VDD2 VI IO IFM PD TA Tstg Ratings -0.5 to +6.0 -0.5 to +120 -0.5 to VDD1 + 0.5 +400, -150 450 1000 -40 to +85 -65 to +150 Note Unit V V V mA mA mW C C Note Simultaneous operation can be performed with up to 4 outputs. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Caution Recommended Operation Ranges (TA = -40 to +85C, VSS1 = VSS2 = 0 V) Parameter Logic section supply voltage Driver section supply voltage High-level input voltage Low-level input voltage Driver output current Symbol VDD1 VDD2 VIH VIL IOH IOL1 IOL2 Diode forward current IFOH IFOL Low capacity Note Conditions MIN. 4.5 30 0.7 VDD1 0 TYP. 5.0 MAX. 5.5 110 VDD1 0.2 VDD1 -100 +300 (+75) -400 +400 Unit V V V V mA mA mA mA mA Note The period of 560 ns MAX. from the falling edge of /LBLK. The value enclosed in parentheses is a reference value. Data Sheet S14575EJ2V0DS 7 PD16344 Electrical Characteristics (TA = 25C, VDD1 = 4.5 to 5.5 V, VDD2 = 110 V, VSS1 = VSS2 = 0 V) Parameter High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Symbol VOH1 VOL1 VOH2 VOL21 VOL22 High-level output voltage VOHD Conditions Logic, IOH = -1.0 mA Logic, IOL = 1.0 mA O1 to O64, IOH = -60 mA O1 to O64, IOL = 200 mA Low capacity Note1 MIN. 0.9 VDD1 0 90 TYP. MAX. VDD1 0.1 VDD1 Unit V V V 100 4 (4) 8 (8) V V V , IOL = 50 mA Note2 O1 to O64, IOH = -400 mA DA = 110 V , 103 105 Low-level output voltage VOLD O1 to O64, IOL = 400 mA DK = 0 V Note2 , 5 7 V Input leakage current High-level input voltage Low-level input voltage Static current consumption IIL VIH VIL IDD11 IDD11 IDD21 IDD21 VI = VDD1 or VSS1 0.7 VDD1 1.0 A V 0.2 VDD1 Logic, TA = -40 to +85C Logic, TA = 25C Driver, TA = -40 to +85C Driver, TA = 25C 500 300 1000 100 V A A A A Notes 1. The period of 560 ns MAX. from the falling edge of /LBLK. The value enclosed in parentheses is a reference value. 2. The current characteristic of the diode built into the output section is indicated. 8 Data Sheet S14575EJ2V0DS PD16344 Switching Characteristics (TA = 25C, VDD1 = 4.5 to 5.5 V, VDD2 = 110 V, Logic CL = 15 pF, Driver CL = 50 pF) Parameter Propagation delay time Symbol tPHL1 tPLH1 Conditions CLK A, B MIN. TYP. MAX. 70 70 /CLR A, B CLK O1 to O64 70 160 160 LE O1 to O64 160 160 HBLK O1 to O64 160 160 /LBLK O1 to O64 200 200 /OE O1 to O64 RL = 20 k 300 160 160 300 O1 to O64 O1 to O64 Low capacity Note1 Note2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 tPHL2 tPHL3 tPLH3 tPHL4 tPLH4 tPHL5 tPLH5 tPHL6 tPLH6 tPHZ tPZH tPZL tPLZ Output rising time Output falling time tTLH tTHL1 tTHL2 Output Nch low-driver capability period Clock frequency fCLK tLA 150 100 400 (280) (560) Note2 from the falling edge of /LBLK Data intake, Duty = 50% Cascade connection, Duty = 50% 15 12 15 MHz MHz pF Input capacity CI Notes 1. The period of 560 ns MAX. from the falling edge of /LBLK. 2. The value enclosed in parentheses is a reference value. Timing Requirements (TA = -40 to +85C, VDD1 = 4.5 to 5.5 V, VSS1 = VSS2 = 0 V) Parameter Clock pulse width Symbol PWCLK(H), PWCLK(L) Latch enable pulse width Blank pulse width PWLE PWHBLK PW/LBLK Clear pulse width Data setup time Data hold time Clock latch time PW/CLR tsetup thold tCLK-LE CLK LE 30 300 600 30 10 10 30 ns ns ns ns ns ns ns Conditions MIN. 30 TYP. MAX. Unit ns Data Sheet S14575EJ2V0DS 9 PD16344 Switching Characteristics Waveform (1/3) 1/fCLK PWCLK (H) PWCLK (L) VDD1 50% CLK 50% 50% VSS1 tSETUP tHOLD A/B (input) VDD1 50% 50% VSS1 tPHL1 tPLH1 B/A (output) VOH1 50% 50% VOL1 tPHL3 tTHL1 tPLH3 tTLH VOH2 VOL2 90% On 10% 90% 10% VDD1 /CLR 50% VSS1 tPHL2 VOH1 B/A (output) 5 50% VOL1 10 Data Sheet S14575EJ2V0DS PD16344 Switching Characteristics Waveform (2/3) VDD1 50% CLK tCLK-LE PWLE VDD1 50% LE 50% VSS1 tPHL4 VOH2 VSS1 90% On tPLH4 VOL2 VOH2 On 10% VOL2 PWHBLK VDD1 HBLK 50% 50% VSS1 tPLH5 tPHL5 VOH2 90% On 10% VOL2 PW/LBLK VDD1 /LBLK 50% 50% tPHL6 tTHL2 tPLH6 VOH2 90% On tLA 10% 10% VOL2 Data Sheet S14575EJ2V0DS 11 PD16344 Switching Characteristics Waveform (3/3) VDD1 /OE 50% 50% VSS1 tPLZ tPZL VOH2 90% On 10% VOL2 90% On tPHZ 10% tPZH VOH2 VOL2 12 Data Sheet S14575EJ2V0DS PD16344 8. PACKAGE DRAWING 100 PIN PLASTIC QFP (14x20) A B 80 81 51 50 detail of lead end S CD R Q 100 1 31 30 F G P H I M J K M N S L S NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.20.2 20.00.2 14.00.2 17.20.2 0.8 0.6 0.320.08 0.15 0.65 (T.P.) 1.60.2 0.80.2 0.17 +0.08 -0.07 0.10 2.7 0.1250.075 55 2.8250.175 S100GF-65-3BA-4 Data Sheet S14575EJ2V0DS 13 PD16344 5 9. SOLDERING CONDITIONS Solder the product under the following recommended conditions. For details of the recommended soldering conditions, refer to information Document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and soldering conditions other than those recommended, please contact one of our sales representatives. Surface Mount Type PD16344GF-3BA: 100-pin plastic QFP(14 x 20) Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 seconds MAX. (210C MIN.), Number of times: 3 MAX., Max day: 7 days (need 10 hours with 125C prebeak after limited day) Caution Do not use two or more soldering methods in combination (except the partial heating method). 14 Data Sheet S14575EJ2V0DS PD16344 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14575EJ2V0DS 15 PD16344 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E) * The information in this document is current as of November, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 |
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